Programmable voltage divider and method for testing the impedance of a programmable element

ABSTRACT

A programmable voltage divider has normal and test modes of operation. The divider includes first and second supply nodes, a divider node that provides a data value, and a first divider element that is coupled between the first supply node and the divider node. The divider also includes a controlled node, a second divider element that has a selectable resistivity and that is coupled between the divider node and the controlled node, and a test circuit that is coupled between the controlled node and the second supply node. During the normal mode of operation, the first and second divider elements generate the data value having a first logic level when the second divider element has a first resistivity, and generate the data value having a second logic level when the second divider element has a second resistivity. The test circuit generates a first voltage at the controlled node during the normal mode of operation, and generates a second voltage at the controlled node during the test mode of operation. The test circuit may generate the first and second voltages by varying its impedance, or by switching in and out one or more fixed voltages.

CROSS-REFERENCE TO RELATED APPLICATIONS

The following pending U.S. patent applications entitled: “An EfficientMethod of Determining Acceptable Resistance of a Blown Fuse,” Ser. No.08/813,525, filed Mar. 7, 1997, and “Method and Apparatus for Checkingthe Resistance of Antifuses,” Ser. No. 08/813,767, filed Mar. 7, 1997,issued Nov. 9, 1999 as U.S. Pat. No. 5,982,656 are related to thepresent application.

TECHNICAL FIELD

The present invention relates generally to electronic circuits, and morespecifically to a programmable circuit that allows one to test theimpedance of a programmable element, such as a fuse, during a test mode,and to a method for performing such a test.

BACKGROUND OF THE INVENTION

Many of today's integrated circuits, such as memory circuits, areprogrammable to operate in one or more particular modes, or to have oneor more particular circuit configurations. An example of the latter typeof circuit is a memory that includes redundant memory columns forreplacing defective array memory columns. When a circuit testerdiscovers a defective array column, it programs the memory such thatwhen an external device addresses the defective column, data is routedto a selected redundant column in a manner that is transparent to theexternal device. Typically, the manufacturer programs such integratedcircuits at the factory before shipping them to customers.

These integrated circuits each typically include a bank of nonvolatile,programmable memory elements that the manufacturer programs to set acircuit in the desired operational mode or circuit configuration.Examples of such elements include electrically erasable and programmableread-only memory (EEPROM) cells, fuses, and antifuses. An integratedcircuit often incorporates into its programmable bank the type ofprogrammable element that is the most similar to other elements orcomponents of the circuit. For example, a Flash-EEPROM device oftenincludes a bank of EEPROM cells, but a dynamic random access memory(DRAM) often includes a bank of antifuses, which are similar instructure to the DRAM storage capacitors. Furthermore, such aprogrammable element typically has a first impedance in an unprogrammedstate, and a second, different impedance in a programmed state. Forexample, an antifuse has a high impedance in an unprogrammed state, andthus is essentially an open circuit, and has a low impedance in aprogrammed state, and thus is essentially a short circuit. Conversely, afuse is essentially a short circuit in an unprogrammed state, and isessentially an open circuit in a programmed state.

But because a programmed element may not always have an impedance thatis within a desired range, the manufacturer often measures theimpedances of the programmed elements in an analog fashion after itfinishes programming the entire programmable bank. The analog testerperforms these measurements sequentially by placing a voltage acrosseach programmed element and measuring the current therethrough. If themanufacture discovers a programmed element that does not have thedesired impedance, it can reprogram the element one or more times untilit has the desired impedance.

A problem with this analog testing technique is that it often takes toolong for high-density integrated circuits. As the number of circuitcomponents in an integrated circuit increases, so does the number ofoperational modes and circuit configurations that the circuit supports.Therefore, the number of programmable elements in the programmable bankalso increases to accommodate the additional operational modes andcircuit configurations. For example, a 4 megabit DRAM may have 20antifuses in its programmable bank, but a 64 megabit DRAM may have 640antifuses. Furthermore, measuring the impedance in an analog fashion isrelatively slow because of the parasitic capacitances associated withthe test path and each programmed element. Thus, increasing the storagecapacity of a DRAM by a factor of 16 can potentially increase the numberof antifuses, and thus the already lengthy testing time, by a factor of32. Additionally, testers that can perform analog measurements are oftenexpensive and complicated to operate in the analog-testing mode.

SUMMARY OF THE INVENTION

In accordance with one aspect of the present invention, a programmablevoltage divider has normal and test modes of operation. The dividerincludes first and second supply nodes, a divider node that provides adata value, and a first divider element that is coupled between thefirst supply node and the divider node. The divider also includes acontrolled node, a second divider element that has a selectableresistivity and that is coupled between the divider node and thecontrolled node, and a test circuit that is coupled between thecontrolled node and the second supply node. The test circuit generates avoltage at the controlled node during the normal mode of operation, andvaries this voltage during the test mode of operation.

In a related aspect of the present invention, the test circuit includesa first switch coupled between the controlled node and the second supplynode and a series combination of a second switch and a voltage source,the series combination coupled in parallel with the first switch. Duringthe test mode, the test circuit opens the first switch and closes thesecond switch.

In another related aspect of the invention, the test circuit includes afirst switch coupled between the controlled node and the second supplynode, and a series combination of a second switch and an impedanceelement, the series combination coupled in parallel with the firstswitch. During the test mode, the test circuit opens the first switchand closes the second switch.

In yet another related aspect of the invention, the test circuitincludes a first switch coupled between the controlled node and thesecond supply node, and a diode coupled in parallel with the firstswitch. During the test mode, the test circuit opens the first switch.

An advantage of the present invention is that it allows faster testingof programmable elements as compared with the prior art. Anotheradvantage is that the present invention allows digital testing ofprogrammable elements instead of analog testing.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of a programmable bank according to afirst embodiment of the invention.

FIG. 2 is a schematic diagram of a programmable bank according to asecond embodiment of the invention.

FIG. 3 is a schematic diagram of a first alternative embodiment of thetest circuit of FIG. 2.

FIG. 4 is a schematic diagram of a second alternative embodiment of thetest circuit of FIG. 2.

FIG. 5 is a schematic diagram of a programmable bank according to athird embodiment of the invention.

FIG. 6 is a schematic diagram of an alternative embodiment of theprogrammable elements of FIGS. 1, 2 and 5.

FIG. 7 is a schematic diagram of a programmable bank according to afourth embodiment of the invention.

FIG. 8 is a schematic block diagram of a memory device that incorporatesa programmable bank according to the present invention.

FIG. 9 is a schematic block diagram of a computer system thatincorporates the memory device of FIG. 8.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1 is a schematic diagram of a programmable bank 10 according to afirst embodiment of the invention. The bank 10 includes individuallyprogrammable circuits 12 ₀-12 _(n), which generate binary referencesignals P₀-P_(n) at respective output nodes 14 ₀-14 _(n). The actuallogic levels of the signals P₀-P_(n) depend upon the states in which thecircuits 12 ₀-12 _(n) are programmed. The integrated circuit (not shownin FIG. 1) that incorporates the bank 10 uses the signals P₀-P_(n) toselect its operational modes or to configure its circuitry. The bank 10also includes a test circuit 16, which allows the manufacturer to testthe programmable circuits 12 ₀-12 _(n) in a digital manner, i.e., bymerely reading the values P₀-P_(n). Thus, the manufacturer can test thebank 10 in a manner that is both faster and easier than prior testingtechniques. Furthermore, the bank 10 may support conventional analogtesting as well as the inventive digital testing. The bank 10 isdiscussed below in greater detail with specific reference to theprogrammable circuit 12 ₀, which is similar in structure and operationto the other programmable circuits 12 ₁-12 _(n).

The programmable circuit 12 ₀ includes a programmable element 18 ₀,which is an antifuse in this first embodiment of the invention. A firstnode of the antifuse 18 ₀ is coupled to a test node 20, which is commonto the first nodes of all the antifuses 18 ₀-18 _(n). A second node iscoupled to an isolation device 19 ₀, which limits the voltage across theantifuse 18 ₀ during normal operation of the bank 10. In one aspect ofthe invention, the device 19 is an NMOS transistor, which has its gatecoupled to a voltage V₁ during normal operation of the bank 10, and to 0V, i.e., ground, during programming of the bank 10.

The circuit 12 ₀ also includes a latch/pull-up circuit 22 ₀, whichgenerates the signal P₀ in response to the state of the antifuse 18 ₀.The circuit 22 ₀ includes an inverter 24 ₀, which has an input terminalcoupled to a reference node 25 ₀. The circuit 22 ₀ also includes afeedback switch 26 ₀, which together with the inverter 24 ₀ forms alatch 27 ₀, an impedance element, e.g., a pull-up or divider device 28₀, and an initialization switch 30 ₀, which allows the circuit 22 ₀ togenerate the desired value for P₀ during the initial power-up of theintegrated circuit that incorporates the bank 10. In one aspect of theinvention, the feedback switch 26 ₀ and the initialization switch 30 ₀are PMOS transistors, and the pull-up device 28 ₀ is acontrolled-current, i.e., long-channel, PMOS transistor. An advantage ofthe circuit 22 ₀ is that after the initialization pulse is removed, thecircuit 12 ₀ draws no quiescent supply current regardless of whether theantifuse 18 ₀ is programmed or unprogrammed.

In addition to the circuits 12 ₀-12 _(n), the programmable bank 10 alsoincludes programming/analog-testing circuitry 32, which is coupledacross each of the antifuses 18 ₀-18 _(n). The programming circuitry 32includes a program/test circuit 34, which provides a programming voltageat the common node 20 to program selected ones of the antifuses 18 ₀-18_(n). A tester (not shown in FIG. 1) can be coupled to the common node20 to provide a test voltage and measure the resultant test current todetermine the impedances of the antifuses 18 ₀-18 _(n) in an analogfashion. A program/decoder 36 couples to ground the first node of anantifuse 18 that is selected for either programming or analog testing.

The bank 10 further includes a bank-mode circuit 37, which includes thetest circuit 16, a normal-mode switch 38, and a conventionalmode-control circuit 44. The switch 38 couples the common node 20 toground during normal operation of the bank 10. The test circuit 16includes a switch 40 that couples the test node to ground through animpedance element 42 in a test mode during digital testing of the bank10. The mode-control circuit 44 controls the switch 38 and the switch 40of the test circuit 16. In one embodiment of the invention, the switches38 and 40 are NMOS transistors, and the impedance element 42 is aresistor. In other embodiments of the invention, the impedance element42 can be a long-channel PMOS transistor or any other conventionalimpedance device.

Still referring to FIG. 1, in operation during programming of theantifuse 18 ₀, the gate of the isolation transistor 19 ₀ is coupled toground such that the transistor 19 ₀ is inactive, and thus electricallyisolates the antifuse 18 ₀ from the latch/pull-up circuit 22 ₀. Thedecoder 36 couples the first node of the antifuse 18 ₀ to ground. Theprogram/test circuit 34 then provides on the common node 20 aprogramming voltage that programs or “blows” the antifuse 18 ₀, i.e.,significantly lowers the impedance between its first and second nodes.In one aspect of the invention, the programming voltage is between 7 Vand 9 V. Once programmed, the antifuse 18 ₀ should be essentially ashort circuit.

During optional and conventional analog testing of the programmedantifuse 18 ₀, the program/test circuit 34 provides a test voltage onthe common node 20, and a conventional tester (not shown in FIG. 1)measures the current through the antifuse 18 ₀. If the measuredimpedance is less than a desired maximum impedance, the antifuse 18 ₀passes the test and is deemed to have been properly programmed. In oneaspect of the invention, the desired maximum impedance is 300 ohms.

During normal operation, the program/test circuit 34 is inactive, andthe decoder 36 uncouples the antifuse 18 ₀ from ground. Furthermore, thegate of the isolation transistor 19 ₀ is coupled to the voltage V₁,which in one embodiment of the invention, is approximately Vcc/2. Thus,if Vcc=5V, V₁=2.5V. In normal operation, the mode-control circuit 44also turns off the transistor 40 to deactivate the test circuit 16, andturns on the switch 38, which couples the common node 20 to ground. Aninitialization pulse then activates the switch 30 ₀ for a timesufficient to set the latch 27 ₀, which generates P₀ equal to logic 1 ifthe antifuse 18 ₀ is programmed, or generates P₀ equal to logic 0 if theantifuse 18 ₀ is unprogrammed. Specifically, during normal operationwhen the initialization pulse is present and the antifuse 18 ₀ isprogrammed to have a low impedance, a relatively large current flowsthrough the switch 30 ₀, the pull-up device 28 ₀, the active isolationtransistor 19 ₀, and the antifuse 18 ₀. The programmable circuit 12 ₀acts as a voltage divider and generates a reference voltage at thereference node 25 ₀. Because the antifuse 18 ₀ has a relatively lowimpedance, which is typically no more that a few hundred ohms, thereference voltage is low enough to represent a logic 0, and thus theinverter 24 ₀ generates P₀ equal to logic 1. The logic 1 at the output14 ₀ of the inverter 24 ₀ turns off the feedback switch 26 ₀. After theinitialization pulse is removed, the inactive feedback switch 26 ₀reinforces the logic 0 at the input of the latch 24 ₀ so that the signalP₀ remains equal to logic 1.

During normal operation when the initialization pulse is present and theantifuse 18 ₀ is unprogrammed to have a high impedance, little or nocurrent flows through the switch 30 ₀, the pull-up device 28 ₀, theisolation transistor 19 ₀, and the antifuse 18 ₀. Thus, the device 28 ₀pulls up the reference voltage at the node 25 ₀ to approximately Vcc,which is high enough to represent a logic 1, and the inverter 24 ₀generates P₀ equal to logic 0, which turns on the feedback switch 26 ₀.After the initialization pulse is removed, the active feedback switch 26₀ reinforces the logic 1 at the input of the latch 24 ₀ so that thesignal P₀ remains equal to logic 0. Furthermore, the isolationtransistor 19 ₀ maintains the voltage at the first node of the antifuse18 ₀ at one threshold voltage below V₁, which as stated above isapproximately Vcc/2 in one aspect of the invention. Thus, the transistor19 ₀ insures that during normal operation, the voltage across theunprogrammed antifuse 18 ₀ is too low to accidentally program it.

In operation during a digital test mode according to the firstembodiment of the present invention, the programmed antifuses 18 ₀-18_(n) are tested to make sure that they are properly programmed, i.e.,that their resistance is less than a desired maximum value. After theantifuse 18 ₀ has been programmed, the programmed resistance of theantifuse 18 ₀ is tested. During testing, the circuit 12 ₀ operates in amanner similar to the normal operating mode described above, except thatthe mode-control circuit 44 shuts off the switch 38, and turns on theswitch 40, thereby coupling the common node 20 to ground through theimpedance element 42. The impedance element 42 effectively increases theimpedance of the antifuse 18 ₀, i.e., increases the impedance of thelower leg of the voltage divider, and thus increases the referencevoltage at the node 25 ₀. Therefore, if the circuit 12 ₀ generates P₀equal to logic 1 when the impedance element 42 is coupled between theantifuse 18 ₀ and ground, then the manufacturer can be virtually certainthat the circuit 12 ₀ will generate P₀ equal to logic 1 during normaloperation when the active switch 38 couples the antifuse 18 ₀ directlyto ground. Conversely, if during the digital test mode the circuit 12 ₀generates P₀ equal to logic 0, then the manufacturer knows that theantifuse 18 ₀ is improperly programmed, or not programmed at all. Atthis point, one can instruct the programming circuitry 32 to reprogramthe antifuse 18 ₀. Or, if the circuit 12 ₀ is expendable, it can belabeled as defective and not used.

For example, if the maximum desired impedance for the antifuse 18 ₀ is300 ohms, and 500 or more ohms between the node 25 ₀ and ground willcause the reference voltage to be equivalent to logic 1 instead of logic0, then the impedance element 42 has a value of approximately 200 ohms.Thus, during the digital test mode, if the impedance of the antifuse 18₀ is greater than the maximum desired impedance of 300 ohms, thecombined impedance between the node 25 ₀ and ground is greater than orequal to 500 ohms, and P₀ equals logic 0. Conversely, if the impedanceof the antifuse 18 ₀ is less than the maximum desired impedance, thecombined impedance is less than 500 ohms, and P₀ equals logic 1.

In one embodiment of the invention, all of the signals P₀-P_(n) arecoupled to a multiplexer (not shown in FIG. 1), which provides aselected one of the signals to an external pin of the device in whichthe bank 10 is incorporated so that a tester can sequentially read thesignals P₀-P_(n) without internally probing the device.

Thus, the digital test mode according to the first embodiment of theinvention allows a manufacturer to use a tester that need only readdigital values instead of measuring an impedance in an analog fashion. Atester that reads only digital values is often less expensive topurchase and operate than one that must measure analog values.Furthermore, such a tester is often easier to operate. Additionally,even a tester that supports both digital and analog testing is ofteneasier and cheaper to operate in the digital mode.

Moreover, the digital technique is often faster than prior analogtechniques. Specifically, in the digital test mode, all the antifuses 18₀-18 _(n) are connected so that the circuits 12 ₀-12 _(n) areoperational. Thus, one need only switch a multiplexer or move a probefrom one signal P to the next, with no delay other than the multiplexerswitching or probe movement time, which are often relatively short.Conversely, in the prior analog testing, each antifuse 18 must beindividually switched into the test circuit. Because of the parasiticcapacitances and inductances associated with the antifuses 18 and thebank 10 in general, after switching each antifuse 18 into the testcircuit, one must wait a relatively long settling time before measuringthe current therethrough. Thus, the greater the number of programmedantifuses 18 being tested, the more time the inventive digital techniquewill save over the prior analog technique.

FIG. 2 is a schematic diagram of a programmable bank 46 according to asecond embodiment of the invention. The bank 46 is similar in structureand operation to the bank 10 of FIG. 1, except that in place of theimpedance device 42, a test circuit 47 includes a voltage source 48,such as a battery, that generates a positive test voltage VT on thecommon node 20 during the digital test mode. The test voltage VT has thesame affect as discussed above for the impedance 42 of FIG. 1 in that itboosts the reference voltage at the node 25 ₀, and thus effectivelyincreases the impedance of the antifuse 18 ₀ during digital testing. Inone embodiment of the invention, VT is between 0.7 V and 1.5 V.

FIG. 3 is a schematic diagram of a test circuit 49 according to a firstalternative embodiment of the invention. Specifically, the test circuit49 can be used in place of the test circuit 47 of FIG. 2. In the testcircuit 49, the voltage source 48 is a forward-biased PN junction diode50, which generates a positive test voltage of approximately 0.7 Vduring the digital test mode when the switch 38 of FIG. 2 is inactive.

FIG. 4 is a schematic diagram of a test circuit 51 according to a secondalternative embodiment of the invention. The test circuit 51 is similarto the test circuit 49 of FIG. 3, except that it includes adiode-connected NMOS transistor 52 instead of a PN junction diode. In arelated embodiment of the invention, the test circuit 51 may include adiode-connected bipolar NPN transistor (not shown in FIG. 4) instead ofthe NMOS transistor 52.

FIG. 5 is a schematic diagram of a programmable bank 54 according to athird embodiment of the invention. The bank 54 is similar to the bank 10of FIG. 1 and the bank 46 of FIG. 2, except that programmable circuits59 ₀ include programmable elements 56 ₀-56 _(n), and a test circuit 55includes a voltage source 58, which generates a negative voltage −VT onthe common node 20 during the digital test mode. In one aspect of theinvention, the elements 56 ₀-56 _(n) are either laser-cutable fuses orelectrically programmable fuses. Thus, unlike the antifuses 18 ₀-18 _(n)of FIGS. 1 and 2, the fuses 56 ₀-56 _(n) have a low impedance whenunprogrammed, and have a high impedance when programmed. Because thefuses 56 ₀-56 _(n) are not antifuses, the programming circuitry 32 andthe isolation transistors 19 of the banks 10 and 46 may be omitted. Inthis case, the fuses 56 ₀-56 _(n) are programmed using conventionalmeans (not shown in FIG. 5) that are external to the device thatincorporates the bank 54. Alternatively, if the fuses 56 ₀-56 _(n) areelectrical fuses, then the bank 54 may include circuitry that is similarto the programming circuitry 32 of FIGS. 1 and 2. But for clarity, FIG.5 includes no programming circuitry. Because the circuit 59 ₀ is similarin structure and operation to the circuits 59 ₁-59 _(n), the operationof the bank 54 is discussed below in greater detail with reference tothe circuit 59 ₀ for clarity.

During optional conventional analog testing of the element 56 ₀, atechnician uses an ohmmeter (both not shown in FIG. 5) to measure theimpedance of the fuse 56 ₀.

During normal operation, the bank 54 operates as described above inconjunction with the bank 10 of FIG. 1 and the bank 46 of FIG. 2, exceptthat the circuit 59 ₀ generates P₀ equal to logic 0 when the fuse 56 ₀is programmed, and generates P₀ equal to logic 1 when the fuse 56 ₀ isunprogrammed. Again, this is because in contrast to the antifuses 18₀-18 _(n) of FIGS. 1 and 2, the fuses 56 ₀-56 _(n) have a high impedancewhen programmed, and a low impedance when unprogrammed.

During a digital test mode, the programmed fuses 56 ₀-56 _(n) are testedto make sure that they are properly programmed, i.e., that theirprogrammed resistance is greater than a desired minimum value. When thefuse 56 ₀ is programmed, the circuit 59 ₀ operates like it does duringnormal mode, except that the mode-control circuit 44 shuts off theswitch 38, and turns on the transistor 40 to activate the test circuit55 and couple the negative test voltage −V_(T) to the common node 20.−V_(T) effectively decreases the impedance of the fuse 56 ₀ and thusdecreases the reference voltage at the node 61 ₀ as compared with normaloperation. Therefore, if the circuit 59 ₀ generates P₀ equal to logic 0when −V_(T) is on the common node 20, then the manufacturer can bevirtually certain that the circuit 59 ₀ will generate P₀ equal to logic0 during normal operation when the active switch 38 couples the commonnode 20 directly to ground. Conversely, if during the digital test modethe circuit 59 ₀ generates P₀ equal to logic 1, then the manufacturerknows that the fuse 56 ₀ is improperly programmed, or not programmed atall. At this point, the manufacturer can reprogram the fuse 56 ₀, or, ifthe circuit 59 ₀ is expendable, can label it as defective and not useit.

For example, using the conventional voltage-divider equation:$V_{r} = {\frac{R_{a}}{R_{a} + R_{b}} \times V}$

where V_(r) is the reference voltage at the node 61 ₀, if Vcc equals 5V, the threshold between logic 1 and logic 0 is approximately 2.5 V, theimpedance of the element 28 ₀ is 10 kilohm, and the desired minimumimpedance of the fuse 56 ₀ is 40 kilohm, then −VT=−7.5 V. Thus, duringthe digital test mode, if the impedance of the fuse 56 ₀ is less thanthe desired minimum impedance, P₀ will equal logic 1. Conversely, if theimpedance of the fuse 56 ₀ is greater than the desired minimumimpedance, P₀ will equal logic 0.

As discussed above in conjunction with FIG. 1, all of the signalsP₀-P_(n) may be coupled to a multiplexer (not shown in FIG. 5), whichprovides a selected one of the signals to an external pin of the devicein which the bank 54 is incorporated so that a tester can sequentiallyread the signals P₀-P_(n).

FIG. 6 is a schematic diagram of nonvolatile programmable element 60according to an alternative embodiment of the invention. Theprogrammable element 60 is a EEPROM cell that includes a floating gate62. In a conventionally defined unprogrammed state, there is no voltagestored on the floating gate 62, and thus the EEPROM cell 60 has a lowimpedance, i.e., acts as a closed circuit, when a voltage is applied toits gate. In a conventionally defined programmed state, a negativevoltage is stored on the floating gate 62, and thus the EEPROM cell 60has a high impedance, i.e., acts as an open circuit, when a voltage isapplied to its gate. Thus, the EEPROM cell 60 is similar to the fuseelements 56 ₀-56 _(n) of FIG. 5, and in one aspect of the invention maybe used in place of these fuse elements in the bank 54.

Still referring to FIG. 6, one can unconventionally define theunprogrammed state as when the floating gate 62 has a negative voltagestored thereon, and the programmed state as when there is no voltagestored on the floating gate 62. Using this unconventional definition,the EEPROM cell 60 resembles the antifuses 18 ₀-18 _(n) of FIG. 1. Thus,in an aspect of the invention using these unconventional definitions ofthe programmed and unprogrammed states, EEPROM cells like the cell 60may be used in place of the antifuse elements 18 ₀-18 _(n) in the bank10 of FIG. 1. If, however, one decides to use this unconventionaltechnique, he has to first “unprogram” all of the cells 60 by storingnegative voltages on the floating gates 62 thereof.

FIG. 7 is a schematic block diagram of a programmable bank 64 accordingto a fourth embodiment of the invention. The bank 64 allows simultaneousdigital testing of more than one programmable circuit 66 ₀-66 ₃ at atime. Although the four circuits 66 ₀-66 ₃ are shown here for clarity,the bank 64 may include more or less of these circuits. Furthermore, inone aspect of the invention, the programmable circuits 66 ₀-66 ₃incorporate antifuses (not shown in FIG. 7), and are thus similar to thecircuits 12 ₀-12 _(n) of FIGS. 1 and 2.

The bank 64 includes a program/test decoder circuit 68, which selectsthe circuits 66 ₀-66 ₃ that are to be programmed during a programmingmode or are to be tested during a conventional test mode. A test circuit70, which is coupled between a node 71 and ground, generates a testvoltage or provides a test impedance during a digital test mode. Thetest circuit 70 may be similar to the test circuits 16 or 47 of FIGS. 1and 2. A normal-mode switch 78 couples the node 71 to ground duringnormal operation of the bank 64. A program/test circuit 72 provides aprogramming voltage during programming of the circuits 66 ₀-66 ₃, andprovides a test voltage during the conventional test mode. In one aspectof the invention, the circuit 72 is a conductive pad to which anexternal test circuit (not shown in FIG. 7) provides the describedprogramming and test voltages. A normal-mode/digital-test-mode switch 74couples a node 76 that is common to the circuits 66 ₀-66 ₃ to the node71 during normal operation and during the digital test mode. Aprogram-mode/conventional-test-mode switch 75 couples the common node 76to the program/test circuit 72 during programming or conventionaltesting of the bank 64. A logic circuit 79 receives the output signalsP₀-P₂ of the circuits 66 ₀-66 ₂, and logically combines them to generateresultant output signals L₀-L₇. A multiplexer 80 provides a selected oneof the signals L₀-L₇ and P₃ to an external terminal of the deviceincorporating the bank 64 during the digital test mode. A mode-controlcircuit 81 controls the operation of the switches 74, 75, and 78, andthe test circuit 70.

During the programming of the circuits 66 ₀-66 ₃, the decoder 68receives address signals at its address inputs and couples the selectedone of the circuits 66 ₀-66 ₃ to ground through a switching network 69.The switch 75 is active, and thus couples the common node 76 to theprogram/test circuit 72. Thus, in a manner similar to that describedabove in conjunction with FIG. 1, the circuit 72 generates a programvoltage and thus programs those of the circuits 66 ₀-66 ₃ that thedecoder 68 selects for programming.

During the conventional test mode, the circuit 72 generates a testvoltage, and external test circuitry measures the current flowingthrough the circuit 66 under test to determine the resistance of theprogrammable element therein and whether or not it has a desired value.

During normal operation, the decoder 68 deactivates the switchingnetwork 69, the switches 74 and 78 are active, and the switch 75 isinactive. The bank 64 thus operates similarly to the banks 10 and 46,except that the signals P₀-P₂ are not considered separately, but areconsidered as a predetermined logical combination. For example, thelogic circuit 79 may generate a selected one of the signals L₀-L₇ equalto logic 1, and the remainder of these signals equal to logic 0, whereeach one of the eight possible combinations of the three signals P₀-P₂selects a different one of the signals L₀-L₇ to equal logic 1. Thus,P₀-P₂ may be used together to select one of eight operational modes orcircuit configurations.

During the digital test mode of operation according to the presentinvention, the tester can test the bank 64 more quickly by reading theappropriate one of the signals L₀-L₇ instead of reading all of thesignals P₀-P₂ individually. Specifically, the decoder 68 disables all ofthe transistors in the switching network 69. The switch 74 is active,and the switches 75 and 78 are inactive so that the test circuit 70 cangenerate a test voltage or provide a test impedance at the common node76. The digital testing then proceeds as discussed above in conjunctionwith FIG. 1. But instead of reading the signals P₀-P₂ individually, thetester reads the one of the signals L₀-L₇ that corresponds to thecorrect programmed combination of P₀-P₂. For example, if the circuits 66₀-66 ₂ are programmed to generate the signals P₀-P₂ equal to logic 1,logic 0, and logic 1, respectively, and this sequence of values causesthe logic circuit 79 to generate L₅ equal to logic 1, and L₀-L_(4 and L)₆-L₇ equal to logic 0, then the tester conventionally controls themultiplexer 80 to couple L₅ to the external read pin. If L₅ equals logic1, then the tester, with just this one reading, determines that all ofthe circuits 66 ₀-66 ₂ are properly programmed. By effectively testingmore than one of the circuits 66 ₀-66 ₃ simultaneously, the testing timecan be significantly reduced as compared with reading the signals P₀-P₃sequentially. In another aspect of the invention, the multiplexer 80 maybe omitted, and the tester can directly probe the outputs of the logicgate L.

FIG. 8 is a schematic block diagram of a memory device 90, whichincorporates a programmable bank 92 according to the present invention.The programmable bank 92 may be similar to one of the banks 10, 46, 54or 64 of FIGS. 1, 2, 5 and 7, respectively. In one embodiment, thememory device 90 is a synchronous dynamic random access memory (SDRAM),although the inventive programmable bank 92 may be used in other typesof memories, and in integrated circuits other than memories, such asmicroprocessors.

In addition to the programmable bank 92, the memory device 90 includesan address register 94, which receives an address from an address busADDRESS. A control logic circuit 96 receives CLK and COMMAND signals,receives the programmed signals P from the programmable bank 92, andcommunicates with and controls the other elements of the memory device90.

A row-address multiplexer 98 receives the address signal from an addressregister 94, and provides the row address to row-addresslatch-and-decode circuits 100 a and 100 b. During read and write cycles,the row-address latch-and-decode circuits 100 a and 100 b activate theword lines of the addressed rows of memory cells in memory banks 102 aand 102 b, respectively. Read/write circuits 104 a and 104 b,respectively, read data from the addressed memory cells in the memorybanks 102 a and 102 b during a read cycle, and respectively write datato the addressed memory cells during a write cycle. A column-addresslatch-and-decode circuit 106 receives the address from the addressregister 94 and provides the column address of the selected memory cellsto the read/write circuits 104 a and 104 b. For clarity, the addressregister 94, the row-address multiplexer 98, the row-addresslatch-and-decode circuits 100 a and 100 b, and the column-addresslatch-and-decode circuit 106 can be collectively referred to as theaddress decoder.

A data input/output (I/O) circuit 108 includes a plurality of inputbuffers 110. During a write cycle, the buffers 110 receive and storedata from the DATA bus, and the read/write circuits 104 a and 104 b,respectively, provide this stored data to the memory banks 102 a and 102b. The data I/O circuit 108 also includes a plurality of output drivers112. During a read cycle, the read/write circuits 104 a and 104 brespectively provide data from the memory banks 102 a and 102 b to thedrivers 112, which in turn provide this data to the DATA bus.

The memory device 90 may also include an optional charge pump 114, whichsteps up the power-supply voltage V_(DD) to a voltage V_(DDP). In oneaspect of the invention, the pump 114 generates V_(DDP) approximately 1V to 1.5 V higher than V_(DD). The memory device 90 may use V_(DDP) tooverdrive selected internal transistors in a conventional manner.

In operation, if the memory device 90 is a SDRAM, then all of the inputsignals and output signals, as well as many of the internal signals, aresynchronized to the CLK signal. The control logic 96, in response to theprogrammed values P from the programmable bank 92, controls theoperational modes of the memory device 90 in accordance with thesevalues. Additionally, the control logic 96 may also configure variouscircuits on the memory device 90 in response to the programmed values P.For example, redundant memory elements may be programmed to beresponsive to addresses of defective elements such as rows or columns ofmemory bits.

Alternatively, the programmable bank 92 may be coupled directly to theseconfigurable circuits, and thus supply the signals P directly thereto.

FIG. 9 is a schematic block diagram of a computer system 120, whichincorporates the memory 90 of FIG. 8. The computer system 120 includescomputer circuitry 124 for performing computer functions, such asexecuting software to perform desired calculations and tasks. Thecomputer circuitry 124 typically includes a processor 125 and the memorydevice 90, which is coupled to the processor 125. One or more inputdevices 126, such as a keypad or a mouse, are coupled to the computercircuitry 124 and allow an operator (not shown) to manually input datathereto. One or more output devices 128 are coupled to the computercircuitry 124 to provide the operator with the data generated by thecomputer circuitry 124. Examples of such output devices 128 include aprinter and a video display unit. One or more data-storage devices 130are coupled to the computer circuitry 124 to store data on or retrievedata from external storage media (not shown). Examples of the storagedevices 133 and the corresponding storage media include drives thataccept hard and floppy disks, tape cassettes, and compact disk read-onlymemories (CD-ROMs). Typically, the computer circuitry 124 includesaddress, data, and command busses and a clock line that are respectivelycoupled to the ADDRESS, DATA, and COMMAND busses and the CLK line of thememory device 90.

From the foregoing it will be appreciated that, although specificembodiments of the invention have been described herein for purposes ofillustration, various modifications may be made without deviating fromthe spirit and scope of the invention. Accordingly, the invention is notlimited except as by the appended claims.

What is claimed is:
 1. A method of testing a plurality of fuse elementshaving a variable impedance, comprising: setting one or more of the fuseelements to a low-impedance state; pulling up a first node of each ofsaid fuse elements to a first reference voltage via a respectiveimpedance element; simultaneously coupling a test voltage to a secondnode of each of said fuse elements; examining a resultant voltage ateach of said first nodes; and determining if each of said examinedresultant voltages is greater than a threshold voltage, and, if so,failing the respective fuse element as having an impedance that is toohigh.
 2. The method of claim 1 wherein said test voltage is greater thana voltage that is coupled to said second node during normal operation ofeach of said fuse elements.
 3. The method of claim 1 wherein saidcoupling comprises coupling a test impedance between said second node ofall of said fuse elements and a reference node.
 4. The method of claim 1wherein said coupling comprises coupling a positive voltage to saidsecond node of each of said fuse elements.
 5. The method of claim 1wherein each of said fuse elements is an antifuse.
 6. A method oftesting a plurality of fuse elements having a variable impedance,comprising: setting one or more of the fuse elements to a high-impedancestate; pulling up a first node of each of said fuse elements to a firstreference voltage via a respective impedance element; simultaneouslycoupling a test voltage to a second node of each of said fuse elements;examining a resultant voltage at each of said first nodes; anddetermining if each of said examined resultant voltages is less than athreshold voltage, and, if so, failing the respective fuse element ashaving an impedance that is too low.
 7. The method of claim 6 whereinsaid test voltage is less than a voltage that is coupled to said secondnode during normal operation of each of said fuse elements.
 8. Themethod of claim 6 wherein said coupling comprises coupling a negativevoltage to the second node of each of said fuse elements.
 9. The methodof claim 6 wherein each of said fuse elements is a laser fuse.
 10. Themethod of claim 6 wherein each of said fuse elements is an electricalfuse.